1. Field of the Invention
The present invention relates to a PLL circuit for generating a clock signal from an input signal, a data detection circuit for identifying and playing back information in an input signal using a PLL circuit, and a disk apparatus such as a magnetic disk apparatus or an optical disk apparatus for playing back information recorded on a magnetic disk or an optical disk using a data detection circuit.
2. Description of the Related Art
Owing to the development of the information technology and the start of ground wave digital broadcasting in recent years and so forth, it is demanded to store and edit a large amount of information including video information. As a storage apparatus for storing such a large amount of information, an optical disk apparatus, a magnetic disk apparatus, a magnetic tape apparatus and like apparatus are used. However, the optical disk apparatus is most superior if editing, random accessing and the durability are taken into consideration. However, an existing DVD (Digital Versatile Disk) apparatus does not have a sufficient capacity for continuous recording of a program of BS (Broadcasting Satellite) digital broadcasting because the DVD has a limited capacity of approximately 5 GB (gigabytes) for one face thereof. Therefore, much effort is directed to investigation for the increase of the capacity of a disk apparatus.
It is a problem to the increase of the recording density of an optical disk and a magnetic disk that, as the recording density increases, the intersymbol interference of the readout signal increases, and this decreases the S/N (signal to noise) ratio of the signal and increases the error rate of the detection information. In order to solve the problem to realize high density recording of the optical disk, decrease of the wavelength of a laser beam, increase of the numerical aperture (NA) and the super-resolution (magnetism, light or medium) are used principally. The techniques just mentioned are directed to decrease of the diameter of a converged beam spot to reduce the influence of the intersymbol interference. Meanwhile, in order to increase the recording density of the magnetic disk, use of a GMR (Giant Magneto-Resistive) head and contact recording are used principally. Also the techniques just mentioned are directed to decrease of the intersymbol interference similarly to those for the optical disk.
The techniques given above, however, have a compatibility problem and an apparatus cost problem. On the other hand, a method of increasing the recording density through PRML (Partial Response Maximum Likelihood) detection which positively utilizes the intersymbol interference has been proposed, and this technique is progressively applied to disk apparatus on the market. Since the technique of increasing the recording density by PRML detection digitally processes a readout signal to raise the detection performance, the compatibility can be assured and also a rise of the cost can be suppressed through application of the LSI technology. The technique is further advantageous in that it can be combined with another technique for increasing the recording density.
The PRML is a detection method which uses PR (Partial Response) a combination of waveform equalization and maximum likelihood detection, and it is well known that the PRML has a high playback performance even from a high density recorded playback waveform having a deteriorated resolution by using maximum likelihood detection based on an intersymbol interference amount of a playback channel. For example, a document Proc. SPIE, vol. 2338, pp.314-318 discloses an optical disk to which the PRML is applied. Where the PRML is applied to an optical disk, a readout signal read out from the optical disk is waveform equalized in advance so that it may be a signal of a particular PR channel and is then converted into digital information by an A/D (Analog to Digital) converter of 8 bits or the like. Naturally, digital equalization may be performed after such A/D conversion. Waveform data after such equalization have a correlation to preceding and following sample values and can be represented in a state transition diagram. A maximum likelihood detector has the state transition incorporated therein and, even if the S/N ratio of time series input data is low, can detect information with a low error rate by selecting such time series input data which satisfies the state transition and besides exhibits a minimum error.
To determine a pattern string of a maximum likelihood from all possible combinations on an actual circuit is difficult in terms of the circuit scale and the working speed. Therefore, such determination is usually realized by performing selection of a path step by step using an algorithm called Viterbi algorithm disclosed in a document IEEE Transaction on Communication, VOL. COM-19, October 1971. A detector which implements the Viterbi algorithm is called Viterbi detector.
A pulse formation circuit including the PRML detection and digital circuits connected to the pulse formation circuit such as an ECC (Error Correction Code) decoder operate in synchronism with a clock, and therefore, a clock signal is required. Since a readout signal of a disk apparatus has a synchronizing clock signal whose frequency is varied by uneven rotation of the spindle or by a very small inclination of the disk, usually a feedback control circuit called PLL (Phase-Locked Loop) for extracting a variation amount from the readout signal to allow follow-up control is required. Conventionally, the PLL is formed using edge position information of a binary pulse signal obtained by threshold detection of an input waveform with a certain threshold level.
However, as the intersymbol interference of the readout signal increases as the recording density onto a disk increases, a problem appears that jitters (fluctuations in time) of the binary pulse signal increase, resulting in, in the worst case, cancellation of the phase locked state of the PLL. Although a large number of simulation results that have a good detection performance, even when a low resolution an input waveform of a low resolution is obtained by the PRML, have been reported, they are based on the premise that a clock signal can be extracted accurately from within the readout signal. However, when the clock signal includes a lot of jitter or when PLL locking is cancelled, wrong information is outputted. In other words, in high density recording/playback, the detection performance of the detector, e.g., such as a PRML detector, relies much upon the follow-up performance of the PLL.
A PLL circuit which satisfies the request for improvement in PLL follow-up performance is disclosed in Japanese Patent Laid-Open No. 2000-182335 or Japanese Patent Laid-Open No. 172250/1998. The PLL circuit disclosed in Japanese Patent Laid-Open NO. 2000-181335 is shown in FIG. 16. Referring to FIG. 16, the PLL circuit includes an equalizer 101 for converting the waveform of an input signal into a waveform of a desired frequency characteristic, an A/D converter 102 for converting the output signal of the equalizer 101 into a digital signal and outputting the digital signal at a timing of a predetermined clock signal, a phase comparator 103 for extracting phase information of the input signal from the output signal of the A/D converter 102 using a plurality of threshold values set in advance, a loop filter 104 for integrating the phase information outputted from the phase comparator 103, a voltage controlled oscillator 105 for outputting the predetermined clock signal whose oscillation frequency is controlled in accordance with an output signal of the loop filter 104, and a maximum likelihood detector 106 for detecting information included in the output signal of the A/D converter 102.
In short, the PLL circuit disclosed in Japanese Patent Laid-Open No. 2000-182335 generates phase information from a plurality of pieces of threshold detection information generated from a plurality of different threshold values to form a phase-locked loop while phase information is conventionally generated based on a threshold detection pulse signal using a single threshold value. The PLL circuit thereby improves the SIN ratio of the output of the phase comparator to improve the PLL follow-up performance.
The PLL circuit disclosed in Japanese Patent Laid-Open NO. 172250/1998 is shown in FIG. 17. Referring to FIG. 17, the PLL circuit includes an A/D conversion circuit 201 for converting an analog signal into a digital signal, an equalizer 202 for equalizing a signal waveform outputted from the A/D conversion circuit 201, a Viterbi detector 203 for discriminating the value of the digital signal waveform-equalized by the equalizer 202 and outputting a digital information signal, a provisional discrimination section 204 for provisionally discriminating a maximum likely value of the digital information signal through maximum likelihood detection and outputting a value corresponding to an amplitude error based on a result of the provisional discrimination, a D/A conversion circuit 205 for converting an output of the provisional discrimination section 204 into an analog signal, a filter 206 for integrating an output of the D/A conversion circuit 205, and a voltage controlled oscillator 207 for controlling the sampling frequency of the A/D conversion circuit 201 based on the error signal from the filter 206.
In short, the PLL circuit disclosed in Japanese Patent Laid-Open NO. 172250/1998 provisionally discriminates through maximum likelihood detection to which one of the reference levels the digital input information is nearest and generates phase information based on the provisional discrimination value and the input signal to form a PLL loop. Consequently, the PLL circuit removes information, which is outputted in error because of noise or the like, from within a phase comparison output based on an ordinary threshold detection pulse signal to improve the S/N ratio of the phase comparator.
However, with the PLL circuit disclosed on Japanese Patent Laid-Open No. 2000-182335, since the distance between adjacent threshold levels decreases as the order of the PR channel becomes higher, there is a problem that the PLL follow-up property is varied significantly by a small amount of offset level variation or the non-linearity of the waveform. Further, from the characteristic of the PR channel, as the order number increases, the absolute value of the differential coefficient of a waveform which passes a certain reference level differs much depending upon preceding and following patterns. Accordingly, there is another problem that, even if the phase displacement is equal, the detection edge timing differs.
Also with the PLL circuit disclosed in Japanese Patent Laid-Open No. 172250/1998, when a high-order PR channel is adopted similarly, since phase information generated from data which is discriminated to have a certain reference level differs significantly depending upon preceding and following patterns, there is a problem that the S/N ratio of phase information is deteriorated. Such problems as described above occur not only with a PLL circuit but also with a data detection circuit which uses a PLL circuit and a disk apparatus which uses a PLL circuit.
It is an object of the present invention to provide a PLL circuit which suffers less likely from follow-up jitters.
It is another object of the present invention to provide a data detection circuit which has a good follow-up characteristic and can detect data accurately.
It is a further object of the present invention to provide a disk apparatus which has a good follow-up characteristic and achieves high density recording and promotion in reliability of playback information.
In order to attain the objects described above, according to the present invention, phase error information of an S/N ratio as high as possible is extracted from a readout signal having a deteriorated resolution and used for PLL control.
More particularly, according to an aspect of the present invention, there is provided a PLL circuit for generating a clock signal from an input analog signal, comprising an A/D converter for sampling the input analog signal to produce a digital signal, a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputting pattern string identification information which indicates an identification result, a phase difference generator for outputting phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter, and control means for generating a clock signal from the phase difference information to control the sampling timing of the A/D converter.
The PLL circuit is thus characterized in that it is estimated by the pattern string detector what type of pattern string an input pattern string of a predetermined length is and a differential coefficient at a sample point is generated based on the pattern string identification discrimination and used to generate phase difference information. Since the phase difference information is generated based on the differential coefficient, sensitive phase difference information is outputted in the proximity of a steep edge whereas little phase different information is outputted where the differential coefficient approaches zero. Accordingly, the PLL circuit can generate or extract phase difference information which is tough against noise and has a high S/N ratio accurately from almost all input sample values. Since the PLL loop is formed based on the phase error information, the PLL circuit can achieve a high follow-up performance.
Preferably, the PLL circuit further comprises an analog equalizer provided in the preceding stage to the A/D converter for performing waveform equalization of the input analog signal. The follow-up performance of the PLL loop can be improved by the analog equalizer.
According to another aspect of the present invention, there is provided a PLL circuit for generating a clock signal from an input analog signal, comprising an A/D converter for sampling the input analog signal at a fixed clock rate to produce a digital signal, an interpolator for adjusting the phase of the digital signal, a pattern string detector for identifying a type of an input pattern string formed from a plurality of successive data values successively outputted from the interpolator and outputting pattern string identification information which indicates an identification result, a phase difference generator for outputting phase difference information which indicates a phase error of the output of the interpolator based on the pattern string identification information and the output of the interpolator, and an interpolation amount calculator for controlling the phase adjustment amount of the interpolator based on the phase difference information.
With the PLL circuit, since it comprises the interpolator, pattern string detector, phase difference generator and interpolation amount calculator, it can be formed as a fully digital PLL circuit which exhibits a good follow-up characteristic.
Preferably, the PLL circuit further comprises a digital equalizer provided between the A/D converter and the interpolator for performing waveform equalization of the output signal of the A/D converter. The follow-up performance of the PLL loop can be improved by the analog equalizer.
In each of the PLL circuits, the pattern string detector may include an error generator for calculating error amounts between the input pattern string and all of ideal pattern strings which the input pattern string can assume, and a minimum value detector for outputting the pattern string identification information representing that the ideal pattern string whose calculated error amount is minimum is an ideal pattern string nearest to the input pattern string.
In this instance, the phase difference generator may include a first memory for storing in advance an ideal value within each of the ideal pattern strings and outputting, when the pattern string identification information is inputted, an ideal value corresponding to the ideal pattern string identification information, and a second memory for storing in advance a differential coefficient of each of the ideal values and outputting, when the pattern string identification information is inputted, a coefficient corresponding to the ideal pattern string identification information, a subtractor for subtracting the ideal value outputted from the first memory from the output of the A/D converter or the output of the interpolator, and a multiplier for multiplying an output of the subtractor by the differential coefficient outputted from the second memory and outputting a result of the multiplication as the phase difference information.
Each of the PLL circuits may further comprise an adder provided between the A/D converter and the pattern string detector and phase difference generator for adding an offset correction amount to the output of the A/D converter and outputting a result of the addition to the pattern string detector and the phase difference generator, and an offset amount learning circuit for learning the offset correction amount to be used to correct the offset amount of the output of the adder from the output of the adder and supplying the learned offset correction amount to the adder. The stability of the PLL loop can be stabilized by the provision of the adder and the offset amount learning circuit.
According to a further aspect of the present invention, there is provided a data detection circuit, comprising any of the PLL circuits recited as above, and a pulse formation circuit for identifying information within the output signal of the A/D converter in synchronism with the clock signal generated by the PLL circuit or the clock signal of the fixed clock.
The application of any of the PLL circuits to the data detection circuit makes it possible for the data detection circuit to exhibit its performance to the utmost.
The pulse formation circuit may include a Viterbi detector. In this instance, preferably the data detection circuit further comprises a reference level learning circuit for learning a reference level of the Viterbi detector from the input and output of the Viterbi detector and outputting the learned reference level to the Viterbi detector and the pattern string detector. The provision of the reference level learning circuit allows correction of a non-linearity or the like of a readout signal which fluctuates comparatively slowly. Consequently, information can be detected further stably.
Preferably, the Viterbi detector is ready for a PR (a, b, b, a) channel and specifically for a PR (a, b, c, b, a) channel.
According to a still further aspect of the present invention, there is provided a magnetic or optical disk apparatus comprising a playback system for a magnetic or optical disk in which the data detection circuit is incorporated. The utilization of the data detection circuit contributes to higher density recording or augmentation of the reliability of playback information of the disk apparatus.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference symbols.